Designing a chip is a complex process. Defining the architectural requirements comes first, followed by developing the microarchitecture, RTL design, and functional verification. The design is then synthesized to create a netlist, which is given to the back-end team so they can perform back-end flow. The netlist undergoes a variety of changes in the back-end flow, including engineering change orders (ECOs), which are carried out on designs after a bug is discovered, and modifications to cells for timing closure. Briefly stated, before the design is taped out, it undergoes a number of changes.
It is necessary to run simulations by providing test cases to validate the design after changes, but this is frequently not possible due to the complexity of the design (complex design requires more runtime), as well as because of the frequency of design changes. The design is then put through logical equivalence checking (LEC), where the tool validates the design by injecting random vectors.
Although there are many tools available in the market to test logical equivalence, Conformal from Cadence and Formality from Synopsys are the most frequently used ones. These tools can be utilized for tasks other than LEC, like ECOs. We’ll walk through the Conformal LEC flow in this article.
Typically, a setup phase is followed by a LEC mode in a conformal LEC flat run flow. The setup mode consists of the following steps:.
There will typically be analog blocks, memories, and digital blocks in a design. When running LEC, different teams provide memories and analog blocks, and they are to be treated as a blackbox. If there are IPs present in the design, the IP provider verifies them; the user is not required to invest time in this process. So, even IPs can be included as blackbox.
Command can be used to specify Blackbox, as seen on line 25 in Figure 2 below. To ensure that only the I/O ports and not the entire design are read, this must be done before reading the design files or library. When we run LEC on large designs, doing so will drastically reduce the runtime and be very helpful. When a block is marked as a “blackbox,” the Conformal tool will check the connections—its inputs and outputs—but not the blackbox’s internal logic.
The Conformal tool also supports reading Verilog standard simulation libraries and Liberty format libraries in addition to supporting Verilog and VHDL for reading design files. The command shown on lines 37 and 40 of Figure 3 below is used to give this information to the tool. By using the appropriate command, the tool can also accept input for the search path and file list.
The built-in Hardware Descriptive Language (HDL) rule check plug-in in Conformal can be used to check for lint errors and warnings after the design has been read in. Depending on the severity, these mistakes and cautions can be reported, and waivers can be added. To report mistakes and alerts in the golden and revised designs, use the commands listed below:
Some ports or pins will be added to the design after design-for-test (DFT) insertion for debugging purposes. For example, scan_in, scan_out, scan_mode, and scan_enable. When comparing RTL vs. Due to these additional ports, the DFT-RTL design would not be equivalent. The design must therefore be put in a common functional mode for both the original and updated versions. This can be achieved by adding constraints to the design.
In Figure 4, for instance, the flop on the right is a scan-enabled D flipflop with a revised design following scan insertion, while the flop on the left is a regular D flipflop in golden design. While the D input in the revised design is a function of Din, scan_in, and scan_enable, the D input in the golden design is a function of Din. Consequently, when the tool passes vectors to both flops, they will be marked as not equivalent. But in functional mode, scan_enable will always be zero. Therefore, the revised design and the golden design will both be equal in functional mode if a constraint is added to scan_enable to tie it to 1’b0.
The netlist generated by the synthesis tool would be power optimized after synthesis. The revised side of Figure 5 below shows how any clock gating logic in the golden design would be changed to latch-based clock gating. Different tools will perform a lot of these optimizations, so it’s important to carefully review them and add modeling directives to match both designs. To add modeling directive for clock gating optimization, run the command below:
The tool must be switched to LEC mode for mapping key points and comparison after all setup restrictions and modeling directives have been added. It’s done by using the following command:.
The tool automatically maps important locations such as primary inputs (PI), primary outputs (PO), DFFs, D-latches, blackboxes, Z-gates, and cut gates when it is in LEC mode. First the tool uses name-based mapping followed by function-based mapping. Name-based mapping, as its name suggests, bases maps on the names of nets and variables in both golden and revised designs. When mapping based on functions, a tool examines the input logic cone of a key point. The tool tries to map key points with name-based mapping before switching to function-based mapping because name-based mapping requires less runtime than function-based mapping.
It is imperative that all key points should be mapped. But not all key points will be mapped when LEC is first run. This is a result of optimizations made by various IC design process tools. For instance, the synthesis tool will change the name of the register from /dma_reg[0][1] in RTL to /dma_0_reg[1] in netlist based on the settings. Given the complexity of the logic cone, function-based mapping may or may not be able to match this critical point, while name-based mapping will be unable to do so. In these circumstances, the tool should be given a renaming rule so that these key points can be mapped. The unmapped key points previously mentioned will be resolved by the following renaming rule:
Comparison will be done only on mapped key points. Therefore, as was previously stated, it is crucial that all key points be mapped. By sending all possible input combinations through the logic cone and observing how the output behaves, the tool will attempt to demonstrate equivalence. The tool will classify important points as equivalent, inverted equivalent, non-equivalent, and abort points after the comparison process. The equivalent key point should be the only category that isn’t debugged. If all of the comparison points are equal, we can say that the golden and revised designs are compatible.
The following command can be used to start the comparison process in LEC mode, and the message shown in Figure 6 will appear after the comparison:
Regression and other complex simulations should not be run every time the design is changed, as was previously discussed. Under these conditions, using the LEC tool, it has been demonstrated that design can be validated with a lot less runtime. The aforementioned procedures for using Cadence Conformal to perform LEC will greatly simplify the process and cut down on debug time.
Disclaimer: The author is not connected to Cadence Design Systems or Synopsys in any way. Any mention of a specific product is not an endorsement or suggestion. The author’s employer, Marvell Technology Inc., does not share the views or opinions that she or he has expressed.
Understanding Logic Equivalence Check in VLSI | What is LEC?
Steps for Logical Equivalence Checks
Let’s examine in detail the various logical equivalence check steps:
In the setup mode, the Conformal tool reads two designs. Golden (synthesized netlist) and Revised (generally, the revised design is the modified or post-processed design that the Conformal tool compares to the Golden design) are the two design types that we designate. The Conformal tool needs three different types of files to run LEC.
The Conformal tool flattens and models the golden and revised designs as setup mode changes to LEC mode, and it automatically maps the key points. The key points are defined as:.
The Conformal tool automatically maps key points during the second stage of equivalence checking and compares them. When the comparison is complete, it pinpoints the differences. Two name-based methods and one no-name method are used by the Conformal tool to map key points. When there have been only minor changes to the logic, name-based mapping can be helpful for gate-to-gate comparisons.
The no-name-mapping method, on the other hand, is helpful when the Conformal tool needs to map designs with entirely different names. When it leaves setup mode, it automatically maps important points using the name-first mapping technique. Unmapped points are the critical points that the Conformal tool does not map.
Unmapped points are classified into three categories:
Comparison comes after the Conformal tool maps the key points in the verification process. Comparison looks at the important details to see if they are equivalent or not. The comparison determines if the compared points are:.
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We can adjust the compare effort to a higher setting in the event of failed compare points. As a result, the Conformal tool can only continue the comparison on the compare points that were abandoned. The Conformal tool shows the total run time and memory used for the comparison as well as the completed run time.
Multiple reports are generated once LEC is completed:
The schedule is too tight to handle blocks with some critical logical failures during the sign-off or tape-out phase. When performing manual fixes or timing ECOs, the logical connectivity can occasionally become corrupted. The tapeout phase will have a high likelihood of a logical breakdown because the physical design engineer will have little opportunity for block closure. Additionally, getting the functional ECO and connecting manually increases the likelihood of breaking logical connectivity. Let’s examine a real-world instance of LEC failure in a block and examine a potential resolution.
First of all, if LEC malfunctions during any of the levels we previously discussed, do not panic. The first thing to do when LEC is failing is to look at the “non-equivalent rpt” file. It’s possible that more cell names are reported in the “non-equivalent” data due to one broken connection. rpt” file.
The cause is that many paths that pass through a single failed or broken connection have all of their endpoints (compare points) reported as “Non-equivalent.”
The first step is to check the non-equivalent file. The 152 compare points that are failing in the LEC are displayed in the sample non-equivalent file below.
These 152 flip-flops reported as non-equivalent are the multibit flops. In multibit flops, two flops are combined to create a single flop with numerous input and output pins. One multibit flop, for instance, will have Q0 and Q1 as output pins and D0 and D1 as input pins if two single bit flops are combined into one.
In reality, only 72 of the 152 flops listed in the report are non-equivalent due to multibit flops. The total number of flops is 722=144 because these are two-bit flops. The remaining are single bit flops.
Next step is to check the unmapped file. This file displays any unmapped nets that lack logical connectivity. We must track the nets to determine where they are missing a connection.
One net (BUFT_net_362908) is not mapped in the design, as can be seen in the above. As seen in Fig. 2, when we check the connection of this net (BUFT_net_362908) in the LEC fail database, we discover that it is only connected to the input pins of another cell (*_364714/A), and the other connection (driver side) of this net is missing as a result of an unintentional cell deletion.
The net reported in the unmapped area is depicted by the highlighted net in the following figure. rpt file.
Here, we can see how the reported net is connected to the LEC fail design.
We are fanning out net (BUFT_net_362908), which is connected to 152 flops in the LEC pass database and reported in an unmapped file.
While the fanout of the net (BUFT_net_362908) reported in the LEC pass database and the 152 flops reported in the non-equivalent file in the LEC fail database, respectively
The actual network connection for this network must now be located in the previous LEC pass database. Checking reveals that the reported net is associated with one inverter that is absent from the LEC fail database.
In order to locate the missing cell, we must backtrack this network in the LEC passed database and examine actual connections.
Do not get confused between un-mapped and non-equivalent reports. While all the cells that are fanouts of this missing cell are visible in the non-equivalent report, only the floating nets of the undriven input pins are visible in the unmapped report.
After determining the cause of the LEC failure, we must replace a missing inverter’s input/output logical connection in the database for the LEC that failed. Fig-3 shows the newly added inverter and its input-output connection. The LEC will now pass if we rerun it, and the non-equivalent report will show zero non-equivalent points.
Equivalency check tools are provided by a number of EDA companies, primarily Formality (Synopsys) and Conformal (Cadence), and are primarily used at the industry level.
Logic Equivalence Check: ASIC design cycle involves a number of stages that vary from functional design to its verification at different levels. As soon as the design is completed and verified through different methodologies is ready to go to a semiconductor chip. Hold on, it’s not simple as it said, one of the most crucial steps is involved while taking RTL design to the chip level. Synthesis, which involves the conversion of RTL design to the equivalent gate-level netlist. This netlist is then used for the physical design implementation.
Once the netlist gets generated it is must to ensure that its functionality is equivalent to the RTL design from which it has been generated. The logical equivalence check performed to ensure the logical equivalency of the gate level Netlist with the RTL design. It can also be performed to check the equivalence of the:
Most of the challenges and the problems are faced in the process are due to logic optimization at the Synthesis stage. The netlist generated during the Synthesis process is finalized after number of process iterations to meet the Timing and Design constraints. These optimizations involves in removing of unused sequential elements and also merging of the sequential elements. As in comparison to the RTL, the netlist can posses different properties if it get generated with clock gating or scan enable sequential elements. One must be look after these main points while doing formal verification:
Comparison will be done only on mapped key points. Therefore, as was previously stated, it is crucial that all key points be mapped. By sending all possible input combinations through the logic cone and observing how the output behaves, the tool will attempt to demonstrate equivalence. The tool will classify important points as equivalent, inverted equivalent, non-equivalent, and abort points after the comparison process. The equivalent key point should be the only category that isn’t debugged. If all of the comparison points are equal, we can say that the golden and revised designs are compatible.
It is imperative that all key points should be mapped. But not all key points will be mapped when LEC is first run. This is a result of optimizations made by various IC design process tools. For instance, the synthesis tool will change the name of the register from /dma_reg[0][1] in RTL to /dma_0_reg[1] in netlist based on the settings. Given the complexity of the logic cone, function-based mapping may or may not be able to match this critical point, while name-based mapping will be unable to do so. In these circumstances, the tool should be given a renaming rule so that these key points can be mapped. The unmapped key points previously mentioned will be resolved by the following renaming rule:
The tool automatically maps important locations such as primary inputs (PI), primary outputs (PO), DFFs, D-latches, blackboxes, Z-gates, and cut gates when it is in LEC mode. First the tool uses name-based mapping followed by function-based mapping. Name-based mapping, as its name suggests, bases maps on the names of nets and variables in both golden and revised designs. When mapping based on functions, a tool examines the input logic cone of a key point. The tool tries to map key points with name-based mapping before switching to function-based mapping because name-based mapping requires less runtime than function-based mapping.
Typically, a setup phase is followed by a LEC mode in a conformal LEC flat run flow. The setup mode consists of the following steps:.
Disclaimer: The author is not connected to Cadence Design Systems or Synopsys in any way. Any mention of a specific product is not an endorsement or suggestion. The author’s employer, Marvell Technology Inc., does not share the views or opinions that she or he has expressed.
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FAQ
What is Conformal LEC?
Conformal Smart LEC analyzes the traits of both the golden and revised designs, such as datapath type and logic complexity, with a single command. The command automatically implements the best strategy to complete the comparison based on the findings of the analysis.
What is LEC check in VLSI?
Introduction. One of the most crucial aspects of the ASIC VLSI design is the Logic Equivalence Check, or LEC for short. To provide a higher level of verification confidence on properties, formal verification techniques have been developed using mathematical proof rather than simulation or test vectors.
What is conformal tool?
The Conformal tool performs LEC between the input golden and revised netlist after reading various optimizations, including boundary optimization and hierarchical clock gating carried out by the synthesis tool. The LEC would report non-equivalent points.
What is conformal in VLSI?
It encircles a specific layer, which may be a conductor or another type of dielectric This indicates that it is not a universal dielectric layer that can be found anywhere. Only in locations where its corresponding layer is present can you find it (the conformal layer). Like POLY, M1 , M2 etc.
