- What is CTS?
- What are the goals of CTS?
- Which metal layer do you prefer for clock routing and why?
- How do you optimize skew/insertion delays in CTS?
- What are the effects of metastability?
- What are the pros and cons of LVT and HVT cells?
- How do you set inter clock uncertainty?
VLSI Physical Design: Clock Tree Synthesis (CTS)
1. Inverters or buffers to be defined which will be used to balance the clock tree. 2. CTS Exceptions (End points of clock tree). 3. Skew group information. 4. Contains target Skew, max target transition and other timing constraints as per clock tree. 5. Top layer and bottom layer route info. VIA’s information which will be used during clock route. 6. Clock related info (Generated clocks {Eg. Clock divider, Clock multiplier etc}). 7. NDR Rule definition.
There are many points present in the design after which we don’t need clock tree propagation. So, to avoid unnecessary buffering, we can ask the tool not to go for balancing further to these points. There are following clock tree exceptions: Stop Pin – No buffer/inverter insertion beyond this point (Don’t touch scenario) Ignore Pin (Float Pins) – No DRV, No Balance Exclude Pin – DRV Fixing but no balancing Through Pin – DRV Fixing as well as Balancing Please visit below link for more details.https://ivlsi.com/clock-tree-synthesis-cts-vlsi-physical-design/
For big designs like 5 mm, 8mm, or 10mm length we can not depend on the typical tool strategies to do clock tree balancing. If we will depend then there will be a very high latency number, and unnecessary buffering will happen then lots of power issues will be there and basically not acceptable clock tree. so to avoid this we create tap points in between this long size design wherever we have pipeline registers placed. In this situation we are not going to do balancing w.r.t clock port but w.r.t tap points which is also named as multi-source CTS points. Looking at these points we do clock balancing. This method we plan with local skew groups and save design from unnecessary buffering.
FAQ
How will you synthesize clock tree?
Why is CTS done before routing?
How does CTS reduce insertion delay?
What are the different steps happens during clock tree optimization?
…
Perform power optimization.
- Use a large/Max clock gating fanout during insertion of the ICG cells.
- Merge ICG cells that have the same enable signal.
- Perform power-aware placement of ICG and registers.
