This phase targets functional feature verification of Analog Mixed Signal design using Digital RTL and Behavioral Analog Design. Standard verification methodologies like UVM, OVM or VMM can be used to verify functional features for Analog Mixed Signal Design. Tool used in this phase of verification depends on Analog behavioral model. Analog behavioral model used here can be designed in Verilog, VHDL or Verilog AMS.
Disadvantage: It depends on test list determined by design and verification team, whereas in case of Digital, it is automated testing using EDA tool. So quality of this verification solely depends on completeness of test list.
Based on methodology used during this phase, functional correctness of design can be measured using similar parameters used for coverage driven verification (CDV). This functional correctness measurement metrics will be solely dependent on approach used for verification. It can be purely directed verification or coverage driven random verification.
Method1: Using Formal Verifier Tool: Create PSL or SVA assertions based on Specification. This formal check targets all connectivity and combinational circuit in design. This method does not require any test case or verification environment development.
This method requires a functional environment to generate various stimuli for design. For design checks describe in Method2 special stimulus generator is required to transmit a signature value on input voltage and bias pin, which will be checked by design checks if behavioral model is in Verilog or VHDL.
People are getting interviews at Cyient through
Prepare for Verification Engineer jobs with interviews advice from real interviews View all interview questions
What is Mixed Signal validation?
Today’s mixed-mode IC designs can be large, task-intensive Systems on Chip that can involve complicated boundary timing. Managing these SoC risk items takes a special skill set to ensure that you have the highest chance of first pass silicon functionality.