The STA introduces OCV (On Chip Variation) analysis before discussing the topic of CRPR (Clock Reconvergence Pessimism Removal), so I’ve included a brief overview of OCV here so that we can understand CRPR and how CRPR relates to OCV.
We all know that during chip manufacturing, variations may occur due to process, voltage, or temperature changes, and as a result, transistors may operate more quickly or more slowly in different dies.
PVT (processor, voltage, and temperature) causes delays to vary across a single die. When it’s cold outside, the IC’s delay value is different than when it’s hot outside. The delay will be reduced because the metals in IC will contract in cold weather. The delay will lengthen in hot weather because the metal will expand.
The variation may be random or deterministic. Oxide thickness variation, implant doses, and metal or dielectric thickness variations are all random variations.
Let’s say there are two inverters with the same characteristics on a single chip, but their delay propagation is different due to process, voltage, and temperature variations.
STA introduces the idea of On-Chip Variation (OCV) to account for these variations. This idea adds additional timing margins to timing analysis. In OCV, a fixed derate value will be added to each cell or net in the launch clock path, data path, and capture clock path, increasing pessimism in timing analysis and compensating for variation.
Simply put, OCV is a method that uses this flat derate to make faster paths faster and slower paths slower. OCV therefore injects some pessimism into the common launch and capture paths. e. There are two delays (min and max) for a single cell.
With this idea, we eliminate the excess pessimism from the common path. Typically, we add the delay to each buffer during the OCV process. To address this, we are removing the delay from the common path during the CRPR process. However, adding more delay also affects the chip’s speed and may result in violations.
The launching and capturing clock paths’ common delay difference is known as CRPR.
Three flip flops, buffers, and combinational circuits in the figure have two delays: one is the minimum delay and the other is the delay after adding derating I. e. max delay. Consider Time period 8ns and Tsetup and Thold are 0. 2ns.
Let’s take a look at a buffer that is positioned in the common data and clock paths for the buf2 and buf3 buffers.
The tool calculates max. delays for setup calculation and min. delays for hold (worst- and best-case analysis).
When comes to OCV analysis, the tool further considers, max. for data path and min. for clock path during setup analysis. max. for clock path and min. for data path during hold analysis.
Consequently, the buffer placed in the common path now has two values, i e. , max. and min. values. We are aware that a cell cannot have two different values at the same time. Thereby we calculate the buffer value as:
We are removing the derating to common buffer during the CRPR process. here the common buffer buf1. so we are considering 0. 70ns-. 60ns =. 10ns for buf1.
It is evident from the results above that the CRPR method is advantageous for both setup and hold.
OCV (on chip variation) will be the subject of a different post because it is unrelated to this one.
On-Chip Variation in VLSI | OCV | Why OCV occur | How to take care of OCV | AOCV | POCV
We construct the inverters on silicon wafers using the photo-lithography fabrication technique, which is a less-than-ideal process because there will be irregularities along the edges. And the reason is that the aforementioned method requires photo-masks, which are made using etching, which is also not ideal. See what an ideal mask and a real mask look like below.
If this inverter is surrounded by a chain of inverters on either side, the variation on the sides will be less because the process parameters to build a mask for a chain of inverters of a similar size are nearly identical. However, these variations on the sides also depend on what logic cell is present on either side of this inverter. However, the variation will be greater if the inverters are surrounded by other gates, such as flip-flops.
Ever wonder which of my earlier posts are interviewers’ go-to rip-off questions? And one of them, specifically for interviews using static timing analysis, is On-Chip Variation (OCV). This analysis is the result of interviews with and recruitment into prominent VLSI industries. Most importantly, the majority of them have benefited from my posts and videos, and I’m extremely proud of that. Nice feeling.
Interview Questions for Child Protective Investigators:
Assesses the candidates work experience.
Let’s say there are two inverters with the same characteristics on a single chip, but their delay propagation is different due to process, voltage, and temperature variations.
We all know that during chip manufacturing, variations may occur due to process, voltage, or temperature changes, and as a result, transistors may operate more quickly or more slowly in different dies.
OCV (on chip variation) will be the subject of a different post because it is unrelated to this one.
Three flip flops, buffers, and combinational circuits in the figure have two delays: one is the minimum delay and the other is the delay after adding derating I. e. max delay. Consider Time period 8ns and Tsetup and Thold are 0. 2ns.
Simply put, OCV is a method that uses this flat derate to make faster paths faster and slower paths slower. OCV therefore injects some pessimism into the common launch and capture paths. e. There are two delays (min and max) for a single cell.
In this article, we’ll talk about the causes of on-chip variation (OCV) in VLSI, why it happens, and how to account for it in physical design. The Advance On Chip Variation (AOCV) and Parametric On Chip Variation (POCV) will also be covered in very brief detail. Background: The final output which … Read more.
On Chip Variation (OCV), Advance On Chip Variation (AOCV), and Parametric On Chip Variation (POCV) have all been compared in this article. It has also been discussed why and how a new variation model has improved on the previous one and how it is better in terms of timing pessimism. Introduction: We have … Read more.
FAQ
What are on chip variations?
On-chip variation (OCV) acknowledges the inherent variability of semiconductor processes and how that variability affects things like logic timing.
How can I lower my OCV?
What is AOCV in VLSI?
Stage-based OCV is also known as Advanced OCV and SBOCV Consider two examples of single and multiple cells to better understand the need for AOCV. Compared to the number of cells in a path, a single cell in isolation displays a greater variation in delay.
