I have a signal that I need to send between two asynchronous clock domains in an FPGA. Both clock domains have the same nominal frequency. The signal will be low most of the time. It will occasionally assert high for several consecutive clock cycles and then go low again for many many clock cycles.
Interview Questions on Clock Domain Crossing CDC and synchronizers Part 1
What is Clock Domain Crossing (CDC)?
Formally Clock Domain Crossing (CDC) in digital domain is defined as: “The process of passing a signal or vector (multi bit signal) from one clock domain to another clock domain.”
A digital circuit with flip flops will always have clocks associated to it and circuits with only one clock domain are normally restricted to elementary school courses. The modern SoCs, with so many dedicated data processing islands usually need to transfer data between these multiple clock domains (islands). When data needs to be transferred between two different clock domains, it will appear to be asynchronous to the new clock domain.
To understand Clock Domain Crossing (CDC), we must understand some basics first.
Clock Domain Crossing (CDC) Basics
A clock domain is defined as part of the design that is driven by either one clock or more clocks that have related to each other. For example, a clock with frequency 10MHz and a divide by 2 clock driven from 10MHz clock are treated as a single clock domain design. However, designs which have two unrelated clocks (different clock frequencies) or clocks from two different sources (even with same frequency) are treated as multiple clock domain designs.
Figure 1: Single Clock domain
Figure 2: Clock Domain Crossing Path
Another fundamental concept to tackle the multiclock designs is metastability. In layman’s terms, metastability is referred as unstable or intermediate state. When applied into the digital design domain, it means that a FF can enter a state where output might not have reached to its final expected value and can oscillate between 0 or 1. The signal will stabilize after some time but that depends on FF type and the PVT conditions. Metastability cannot be avoided in digital design but can be handled properly by using different Clock Domain Crossing (CDC) techniques (discussed later) so that proper functionality of the design is intact.
For proper operation of the flip flops, the inputs and clocks must satisfy the setup and hold requirements of the FFs. In figure 2 above, the signal A is asynchronous to destination clock domain, since there is no relation between clk_A and clk_B. Once an asynchronous signal is encountered into a clock domain, the setup and hold timings constraints are very unlikely to be met, and thus the FF can enter a metastable state. In picture below the output A of the FF-A changes very close to the pos-edge of the clk_B and thus violates the setup of the FF-B. The output of FF-B will go into metastable state and thus cannot settle to either 1 or 0. This can lead the downstream FFs in the clk_B domain sample wrong value or worse go into metastable state as well.
Figure 3: Setup/hold violation leading to metastability
Metastability occurrence of a given FF can be predicted by using a parameter called MTBF (Mean Time Between Failure) and is measured in years. Without going into much of the math, the conclusion is that it is possible to calculate MTBF given that we know the data rate at the input of the FF and the clock frequency of the FF.
Now as we understand metastability and its causes, we can look what are different techniques we can use to handle these situations in digital design.
What is Metastability?
Any discussion of clock domain crossing (CDC) should start with a basic understanding of metastability and synchronization. In layman’s terms, metastability refers to an unstable intermediate state, where the slightest disturbance will cause a resolution to a stable state. When applied to flip-flops in digital circuits, it means a state where the flip-flop’s output may not have settled to the final expected value.
One of the ways a flip-flop can enter a metastable state is if its setup or hold time is violated. In an asynchronous clock domain crossing (CDC), where the source and destination clocks have no frequency relationship, a signal from the source domain has a non-zero probability of changing within the setup or hold time of a destination flip-flop it drives. Synchronization failure occurs when the output of the destination flip-flop goes metastable and does not converge to a legal state by the time its output must be sampled again (by the next flip-flop in the destination domain). Worse yet, that next flip-flop may also go metastable, causing metastability to propagate through the design!
FAQ
What are clock domain crossing techniques?
How do you fix clock domain crossing?
- Conventional two flip-flop synchronizer.
- Toggle synchronizer.
- Handshake based pulse synchronizer.
- Gray encoding for multi bits signal.
- Recirculation mux synchronization.
- Handshake synchronization.
- Asynchronous FIFO synchronization.
- Related articles :
What are different ways to synchronize between two clock domains?
- Conventional two flip-flop synchronizer.
- Toggle synchronizer.
- Handshake based pulse synchronizer.
- Gray encoding for multi bits signal.
- Recirculation mux synchronization.
- Handshake synchronization.
- Asynchronous FIFO synchronization.
- Related articles :
How do you handle clock domain crossing in FPGA?
- Conventional two flip-flop synchronizer.
- Toggle synchronizer.
- Handshake based pulse synchronizer.
- Gray encoding for multi bits signal.
- Recirculation mux synchronization.
- Handshake synchronization.
- Asynchronous FIFO synchronization.
- Related articles :
